Field of the Invention
This invention relates to semiconductor manufacturing technology and more particularly to methods of increasing the yield of semiconductor products by recovering and reworking semiconductor devices which when initially processed have defects or faults in interconnect metallurgy causing devices to be unsuitable for use.
Background of the Invention
The manufacture of semiconductor devices includes several hundred processing steps. Although the yield for each process step may be very high, the cumulative yield can be low. Thus, each process step needs to be optimized to obtain productive yield. A common practice, suitable for many process steps, is that of xe2x80x9creworkingxe2x80x9d or returning processed product to an earlier point in a process to repeat the step or steps which were detected to have not been performed properly.
Not all process steps are subject to being reworked since the changes induced by the particular process must be reversible. That is, the product must be capable of having the effects of the process removed. Photoresist processing is one of the simplest process steps to rework. Another process area where rework has been utilized is in the interconnect metallurgy commonly referred to as Back End Of Line (BEOL) area.
Typically, semiconductor devices have used aluminum-based lines, tungsten studs and silicon dioxide-based insulators which are relatively easy to rework. Two common approaches have been used to rework aluminum-based BEOL. The first method utilizes a plurality of material selective etchants to sequentially remove particular materials. Exposed metal may be etched followed by etching of exposed insulator and so on until the desired starting point is reached. Many semiconductor processing technologies utilize as many as five or six levels of metalization.
The second method of reworking, only recently developed, uses Chemical-Mechanical-Planarization (CMP) to remove entire levels of metal and insulator. Common to both of these techniques is the removal of the entire level of metallurgy comprising metal and it""s respective InterLevel Dielectric (ILD) so that the semiconductor wafer may be returned to the process line to have the entire ILD/metal reapplied.
The emergence of copper-based metallurgy as a replacement for aluminum-tungsten-based metallurgy has posed a number of problems in its manufacture, not the least of which is rework of the BEOL process sequence.
Accordingly, it is an object of this invention to provide a practical rework process for BEOL processing of copper which allows repair at any level of metallurgy.
It is another object to provide reworked semiconductor devices without altering the function or reliability of the finished semiconductor device.
It is yet another object of this invention to provide a method for reworking copper metallurgy which is formed by the inlaid or Damascene process.
It is still another object of this invention to provide a BEOL rework process which can be implemented at any point in the manufacturing process.
These and other objects are achieved by a combination of etch and CMP process steps which provide accurate control of the removal of materials suitable to a copper Damascene technology currently being introduced into manufacturing.
Briefly, the invention includes the steps of etching exposed regions of insulator, CMP removal of the conductor level, CMP removal of any liner material and a substantial portion of any vertical interconnect or via material. These steps are repeated until the lowest level of conductor to be removed is reached. Removal of the ILD and via metal is stopped prior to removing the entire level. Following the removal of the upper regions of the substrate, a barrier layer is applied and then regular BEOL processing steps are carried out by forming a new layer of ILD and conductor.
These and other objects of the invention will be more apparent to those skilled in the art when viewed in conjunction with the accompanying drawings and the preferred embodiment.